ML4800CP【PDF 11/14 页】IC PFC CTRLR AVERAGE CURR 16DIP

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Sheet目录45

7页 8页 9页 10页 [11页]12页 13页 14页

PRODUCT SPECIFICATION

ML4800

REV. 1.0.5 9/25/01

where C

is the required soft start capacitance, and t

DELAY

is the desired start-up delay.

It is important that the time constant of the PWM soft-start

allow the PFC time to generate sufcient output power for

the PWM section. The PWM start-up delay should be at least

5ms.

Solving for the minimum value of C

Caution should be exercised when using this minimum soft

start capacitance value because premature charging of the SS

capacitor and activation of the PWM section can result if

is in the hysteresis band of the V

OK comparator at

start-up. The magnitude of V

at start-up is related both to

line voltage and nominal PFC output voltage. Typically, a

1.0礔 soft start capacitor will allow time for V

and PFC

out to reach their nominal values prior to activation of the

PWM section at line voltages between 90Vrms and

265Vrms.

Generating V

The ML4800 is a voltage-fed part. It requires an external

15V, ?0% (or better) shunt voltage regulator, or some other

regulator, to regulate the voltage supplied to the part at

15V nominal. This allows low power dissipation while at the

same time delivering 13V nominal gate drive at the PWM

OUT and PFC OUT outputs. If using a Zener diode for this

function, it is important to limit the current through the

Zener to avoid overheating or destroying it. This can be

easily done with a single resistor in series with the Vcc pin,

returned to a bias supply of typically 18V to 20V. The

resistors value must be chosen to meet the operating current

requirement of the ML4800 itself (8.5mA, max.) plus the

current required by the two gate driver outputs.

EXAMPLE:

With a V

BIAS

of 20V, a V

of 15V and the ML4800 driving

a total gate charge of 90nC at 100kHz (e.g., 1 IRF840

MOSFET and 2 IRF820 MOSFETs), the gate driver current

required is:

Choose R

BIAS

= 240&.

The ML4800 should be locally bypassed with a 1.0礔

ceramic capacitor. In most applications, an electrolytic

capacitor of between 47礔 and 220礔 is also required across

the part, both for ltering and as part of the start-up bootstrap

circuitry.

Css 5ms

25礎

1.25V

-------------- -

?/DIV>

100nF

(6a)

GATEDRIVE

100kHz 90nC

?/DIV>

9mA

(7)

BIAS

+ +

---------------------------------

(8)

BIAS

20V 15V

6mA 9mA 5mA

-------------------------------------------------- 250&

Figure 4. Typical Trailing Edge Control Scheme

RAMP

VEAO

TIME

VSW1

TIME

REF

OSC

DFF

CLK

RAMP

CLK

SW2

SW1

VIN

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